VLSI Design
RTL to GDSII, front-end, back-end, DFT and analog layout services.
What we deliver.
Full-spectrum VLSI design services covering RTL design and verification, physical design, static timing analysis, DFT insertion and custom analog layout. We support fabless semiconductor teams, IP vendors and university programs targeting technology nodes from 180nm down to 5nm.
- Experienced across TSMC, GlobalFoundries, SMIC and Samsung PDKs.
- SystemVerilog / UVM verification environments with functional coverage sign-off.
- Physical design flows through Synopsys ICC2 and Cadence Innovus.
- Complete DFT insertion, scan, MBIST, JTAG and ATPG pattern generation.
Start a vlsi design project
Send us a brief, we'll come back with a milestone plan and a fixed price within 48 hours.
Request a ProposalEverything we do under VLSI Design.
RTL Design
Micro-architecture definition, SystemVerilog RTL, low-power (UPF) intent and CDC-clean modules.
Functional Verification
UVM testbenches, constrained-random stimulus, functional coverage and formal property checking.
Physical Design
Floorplanning, placement, CTS, routing and signoff through PnR and DRC/LVS clean.
STA & Signoff
PrimeTime setup/hold closure, multi-corner multi-mode analysis and ECO implementation.
DFT Insertion
Scan compression, MBIST, boundary scan (JTAG) and ATPG pattern generation with high coverage.
Analog & Custom Layout
Op-amps, PLLs, LDOs, bandgaps and standard cells, matched, guard-ringed and DRC/LVS clean.
A predictable four-stage flow.
Spec & Architecture
Micro-architecture, interface protocols, power intent and verification plan agreed with client.
RTL & Verification
RTL coded, lint-clean, CDC-clean and taken through UVM verification to coverage targets.
Physical Implementation
PnR, CTS, routing, STA closure and signoff through DRC, LVS and antenna checks.
Tape-Out Handover
GDSII, netlists, timing reports, coverage reports and full documentation released for tape-out.
Deliverables
- ✓SystemVerilog RTL
- ✓UVM testbench and coverage database
- ✓Synthesis netlist and reports
- ✓Physical GDSII
- ✓STA and signoff reports
- ✓DFT scan patterns
- ✓Tape-out sign-off package
Tools & technologies
Questions we hear often.
Do you own EDA tool licenses?+
Yes, we maintain licensed seats of Synopsys and Cadence tools for internal development, and can also operate inside the client's own tool environment via secure VPN.
What technology nodes do you support?+
180nm, 130nm, 90nm, 65nm, 40nm, 28nm, 16nm, 7nm and 5nm, across TSMC, GlobalFoundries, SMIC and Samsung foundry PDKs.
Can you take a design all the way to tape-out?+
Yes. We deliver GDSII with signed-off DRC, LVS, STA and DFT patterns, coordinated with the foundry's tape-out checklist.